Design guidelines for high-speed Transmission-gate latches: Analysis and comparison

In this paper we present a pencil-and-paper procedure to design transmission-gate latches for high-speed performance. The procedure, based on the Logical Effort approach, independently optimizes the master and slave section to get minimum delay, sizing all transistors in the critical path. The other devices, like keeper transistors or switches in the positive feedback networks, are sized with minimum width thus providing only a negligible capacitive load to the internal nodes. Simulations are performed on a PowerPC 603 master-slave latch designed with a 90-nm technology provided by STMicroelectronics, and the overall good performance of the proposed procedure compared to other design strategies is verified.