Title :
Impact of shielding line on CDM ESD robustness of core circuits in a 65-nm CMOS process
Author :
Ker, Ming-Dou ; Lin, Chun-Yu ; Chang, Tang-Long
Author_Institution :
Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
The charged-device-model (CDM) ESD robustness of core circuit with/without the shielding line was studied in a 65-nm CMOS process. Verified in silicon chip, the CDM ESD robustness of core circuit with the shielding line was degraded. The damage mechanism and failure location of the test circuits were investigated in this work.
Keywords :
CMOS integrated circuits; electromagnetic shielding; electrostatic discharge; failure analysis; integrated circuit modelling; integrated circuit reliability; CDM ESD; CMOS process; charged-device model; core circuits; damage mechanism; failure location; shielding line; silicon chip; size 65 nm; test circuits; CMOS process; Couplings; Electrostatic discharge; Layout; Logic gates; Robustness; Transient analysis; Charged-device model (CDM); ESD; shielding line;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2011.5784565
