DocumentCode
3381521
Title
Test Chip design for study of CDM related failures in SoC designs
Author
Olson, Nicholas ; Shukla, Vrashank ; Rosenbaum, Elyse
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2011
fDate
10-14 April 2011
Abstract
During CDM-ESD testing, SoC (System on a Chip) designs may fail either in the pad ring or in the core circuitry, particularly at the power domain crossings. A specially designed test chip allows one to locate the sites at which ESD-induced damage occurs and also to investigate the efficacy of different CDM protection strategies.
Keywords
design; system-on-chip; CDM related failures; CDM-ESD testing; SoC designs; system on a chip; test chip design; Driver circuits; Electrostatic discharge; Logic gates; MOS devices; Receivers; Stress; Testing; CDM; ESD; System on a chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location
Monterey, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-9113-1
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2011.5784566
Filename
5784566
Link To Document