VLSI implementation of high-speed low power decimation filter for LTE sigma-delta A/D converter application

A high-speed low power decimation filter, as a part of a broadband and high resolution sigma-delta A/D converter, is implemented in SMIC 130nm 1P8M CMOS technology. The decimation filter consists of a comb filter and two half-band filters (HBF). Its power consumption is reduced by adopting poly-phase decomposition technique, multiplierless filter architecture and hardware reusage. With a 500MHz sampling frequency, the decimation filter achieves a signal-to-noise ratio of 63.6dB over 20MHz signal bandwidth, while dissipating 4.8mW and occupying an area of 0.12 mm².