PASIC: a smart sensor for computer vision

Author

Chen, Keping ; Åström, Anders ; Danielsson, Per-Erik

Author_Institution

LSI Design Center, Linkoping, Univ., Sweden

Volume

ii

fYear

1990

fDate

16-21 Jun 1990

Firstpage

286

Abstract

The processor, A/D converter, sensor integrated circuit (PASIC) prototype chip, which contains 256×256 photosensors, a linear array of 256 A/D converters, two 256 8-b shift registers a 256-bit-serial arithmetic logic unit, and a 256×128-b-dynamic RAM, is presented. It is claimed to be a viable architecture for low-level vision processing. The processors operate in single-instruction multiple-data (SIMD) mode at 20 MHz. When executing an edge-detection algorithm, it is shown that the 256 processors are capable of an output rate of 3 Mpixel/s

Keywords

computer vision; computerised picture processing; digital signal processing chips; electric sensing devices; image sensors; integrated circuits; photodetectors; 20 MHz; 256-bit-serial arithmetic logic unit; 32768 bit; 8 bit; A/D converter; ADC; IC prototype chip; PASIC; RAM; SIMD processors; computer vision; low-level vision processing; sensor integrated circuit; serial ALU; shift registers; smart sensor; Arithmetic; Computer architecture; Computer vision; Intelligent sensors; Logic arrays; Logic circuits; Prototypes; Read-write memory; Sensor arrays; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Pattern Recognition, 1990. Proceedings., 10th International Conference on

Conference_Location

Atlantic City, NJ

Print_ISBN

0-8186-2062-5

Type

conf

DOI

10.1109/ICPR.1990.119371

Filename

119371