A fetch-and-op implementation for parallel computers

Author

Lipovski, G.J. ; Vaughan, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA

fYear

1988

fDate

30 May-2 Jun 1988

Firstpage

384

Lastpage

392

Abstract

A fetch-and-op circuit is described. A bit-serial circuit-switched implementation requires only five gates per node in a binary tree. This circuit is also capable of test-and-set primitives (priority circuits) and swap operators, as well as AND and OR operations used in SIMD (single-instruction, multiple-data-stream) tests such as branch on all carries set. It provides an alternative implementation for the combining fetch-and-add circuit to the one designed for the Ultracomputer project; this implementation is suited to SIMD computing and can be adapted to MIMD (multiple-instruction, multiple-data stream) computing

Keywords

multiprocessor interconnection networks; parallel architectures; parallel machines; synchronisation; MIMD; SIMD computing; bit-serial circuit-switched implementation; fetch-and-op circuit; fetch-and-swap operation; modified carry lookahead network; parallel computers; priority circuits; swap operators; synchronisation mechanisms; Application software; Binary trees; Circuit testing; Clocks; Computer networks; Concurrent computing; Delay; Flip-flops; Operating systems; Switches; Synchronization; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architecture, 1988. Conference Proceedings. 15th Annual International Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

0-8186-0861-7

Type

conf

DOI

10.1109/ISCA.1988.5249

Filename

5249