DocumentCode
3381749
Title
An analysis on a pseudo-differential dynamic comparator with load capacitance calibration
Author
Paik, Daehwa ; Miyahara, Masaya ; Matsuzawa, Akira
Author_Institution
Dept. of Phys. Electron., Tokyo Inst. of Technol., Tokyo, Japan
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
461
Lastpage
464
Abstract
This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived. This analysis enhances understanding of the roles of a transistor´s parameters in a pre-amplifier´s gain. Based on the calculated gain, a load capacitance calibration method is analyzed. The analysis helps designers´ estimation for the accuracy of the calibration and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with the simulation results.
Keywords
CMOS integrated circuits; calibration; comparators (circuits); preamplifiers; CMOS technology; dynamic pre-amplifier; load capacitance calibration; pseudo-differential dynamic comparator; size 90 nm; Artificial intelligence; Clocks; Thermal analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157221
Filename
6157221
Link To Document