A time-domain flash ADC immune to voltage controlled delay line non-linearity

A Flash analog-to-digital converter (ADC) architecture operating in time-domain is presented. The proposed ADC uses voltage controlled delay lines (VCDLs) and time-domain comparators instead of pre-amplifiers and voltage-domain comparators in the conventional Flash ADC. Due to the time-domain operation, the proposed Flash ADC benefits from fast switching speed of advanced CMOS process. A key property of the proposed ADC is that its linearity is not affected by the non-linearity of the VCDL, due to the identical VCDLs that are used in both the input signal and reference voltages.