A sliding memory array processor for low level vision

A mesh-connected architecture, called a Sliding Memory Plane (SliM) array processor, for low-level vision tasks is described. SliM alleviates several disadvantages of existing mesh-connected architectures. It is a fine-grained massively parallel single-instruction multiple-data architecture. The inter-PE communication can occur without interrupting PEs. Two I/O planes can provide a buffering capability. The communication and I/O overheads can each be overlapped with the computation, and both are therefore greatly diminished. Bit-serial communication and bit-parallel computation are used. Various types of communication and virtual interconnections for communication between diagonal-direction PEs are provided. Each PE can operate separately, based on some degree of local autonomy. SliM shows thorough applicability with these configurations. Parallel algorithms for low-level vision tasks on SliM having a zero or an O(1) communication complexity are proposed. The performance of SliM is illustrated with several examples of low-level computer vision tasks