DocumentCode
3381925
Title
Analysis of Edge Wordline Disturb in multimegabit charge trapping flash NAND arrays
Author
Zambelli, Cristian ; Chimenton, Andrea ; Olivo, Piero
Author_Institution
Dipt. di Ing., Univ. degli Studi di Ferrara, Ferrara, Italy
fYear
2011
fDate
10-14 April 2011
Abstract
The Edge Wordline Disturb (EWD) represented a reliability issue on traditional Flash NAND memories, evidenced as an unwanted positive threshold voltage shift of all the cells belonging to the first wordline (WL0) connected to the Ground Select Transistor (GSL). In this work, throughout the experimental characterization of Multimegabit arrays it has been investigated the presence and the physical nature of the EWD in Charge Trapping (CT) NAND Flash, emphasizing its dependency on parameters such as the programming voltage, the inhibit voltage and device aging.
Keywords
NAND circuits; electron traps; flash memories; integrated circuit reliability; device aging; edge wordline disturb; flash NAND memory; ground select transistor; multimegabit charge trapping flash NAND array; programming voltage; reliability; threshold voltage shift; Electron traps; Flash memory; Logic gates; Programming; Threshold voltage; Transistors; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location
Monterey, CA
ISSN
1541-7026
Print_ISBN
978-1-4244-9113-1
Electronic_ISBN
1541-7026
Type
conf
DOI
10.1109/IRPS.2011.5784587
Filename
5784587
Link To Document