Title :
A multi-mode 1-V DAC+filter in 65-nm CMOS for reconfigurable (GSM, TD-SCDMA and WCDMA) transmitters
Author :
Li, Li ; Ma, Jun ; Guo, Yawei ; Cheng, Xu ; Zeng, Xiaoyang
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
A 10 bit current-steering DAC and a fourth-order low-pass reconstruction filter are realized in a 65nm CMOS technology to be embedded in multi-standard wireless transmitters. The proposed block meets the specifications of GSM, TD-SCDMA and WCDMA by digitally adjusting the DAC conversion frequency and the low-pass filter cut-off frequency. As result, the power consumption is optimized according to the operation mode and is 2.8mW in GSM and TD-SCDMA modes, 3.6mW in WCDMA mode. For all considered standards, the SFDR is larger than 75dB, which satisfies all specifications of the standard mentioned above.
Keywords :
CMOS integrated circuits; cellular radio; code division multiple access; digital-analogue conversion; low-pass filters; radio transmitters; time division multiplexing; CMOS technology; DAC conversion frequency; GSM; SFDR; TD-SCDMA; WCDMA; current-steering DAC; fourth-order low-pass reconstruction filter; low-pass filter cut-off frequency; multimode DAC; multistandard wireless transmitter; power 2.8 mW; power 3.6 mW; power consumption; reconfigurable transmitter; size 65 nm; voltage 1 V; word length 10 bit; GSM; Multiaccess communication; Spread spectrum communication; Transmitters;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157232
