DocumentCode
3382033
Title
A real time FFT chip set: architectural issues
Author
Ruetz, Peter A. ; Cai, Mike M.
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
Volume
ii
fYear
1990
fDate
16-21 Jun 1990
Firstpage
385
Abstract
The tradeoffs involved in the design of a real-time 40-MHz fast Fourier transform (FFT) chip set are discussed. Tradeoffs involving the algorithmic organization, device partitioning, the data format, and device architecture are examined. The chip set can compute FFTs with up to 2048 points at 40-MHz data rates (or 80-MHz data rates for real data) by using up to 20 chips or at 3-MHz rates when using only three devices. The 1.5-μ CMOS chip set has been designed, fabricated, and tested and is fully functional
Keywords
CMOS integrated circuits; computerised picture processing; digital signal processing chips; fast Fourier transforms; real-time systems; 40 MHz; CMOS chip set; DSP chips; FFT; algorithmic organization; computerised picture processing; data format; data rates; fast Fourier transform; real-time; Computer architecture; Cost function; Digital signal processing chips; Flexible printed circuits; Large scale integration; Logic devices; Partitioning algorithms; Read only memory; Shift registers; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Pattern Recognition, 1990. Proceedings., 10th International Conference on
Conference_Location
Atlantic City, NJ
Print_ISBN
0-8186-2062-5
Type
conf
DOI
10.1109/ICPR.1990.119387
Filename
119387
Link To Document