Title :
High-speed CMOS track-and-hold with an offset cancellation replica circuit
Author :
Azarmehr, Mahzad ; Rashidzadeh, Rashid ; Ahmadi, Majid
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Windsor, Windsor, ON, Canada
fDate :
May 30 2010-June 2 2010
Abstract :
The trade-off between pedestal error and acquisition time limits the level of speed-accuracy that can be achieved by CMOS track-and-hold circuits. This paper presents a circuit technique to design a high-resolution, high-speed T/H circuit. The sampling error produced by clock feedthrough and the charge injection of CMOS switches are eliminated through a cancellation technique using a replica circuit. Simulation results using CMOS 90 nm process confirm that the proposed method lowers the pedestal error considerably and supports linearity over 9.8 effective bits at 500 MHz sampling rate for input signals up to 10 MHz.
Keywords :
CMOS analogue integrated circuits; sample and hold circuits; semiconductor switches; CMOS switches; acquisition time; charge injection; clock feedthrough; frequency 500 MHz; high-resolution high-speed T/H circuit design; high-speed CMOS track-and-hold circuit; offset cancellation replica circuit; pedestal error; sampling error; size 90 nm; word length 9.8 bit; Circuit noise; Clocks; Computer errors; Energy consumption; Error correction; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537545
