Title :
An ASIC-architecture for VLSI-implementation of the RBN-algorithm
Author :
Gijbels, Toon ; Van Eycken, Luk ; Oosterlinck, Andre ; Note, Stefaan ; Catthoor, Francky
Author_Institution :
Catholic Univ., Leuven, Belgium
Abstract :
An optimized recursive binary nesting (RBN) algorithm for coding true color documents is presented. The RBN compression in which algorithm is a segmentation algorithm in which a picture is subdivided into regions with equal properties and for each region only the relevant information for the human eye is kept. Thus, the compressed image consists of segmentation information and the information of the picture behavior in those regions. The picture is subsampled on a quadtree based lattice (segmentation information). The inner pixels are approximated with the use of four lattice corner pixels (pictorial behavior). The subdivision in blocks has to be a function of the image contents. The size of the initial blocks is 65×65. Each pixel in the block is approximated as a weighted average of the four corner pixels (bilinear interpolation). The efficient VLSI architecture used to implement the algorithm is termed the lowly multiplexed cooperating data-path style. Several other designs under consideration are briefly reviewed
Keywords :
VLSI; application specific integrated circuits; computer vision; data compression; digital signal processing chips; encoding; ASIC; RBN-algorithm; VLSI architecture; computer vision; data compression; image segmentation; quadtree based lattice; recursive binary nesting; Algorithm design and analysis; Channel capacity; Color; Compression algorithms; Costs; Image segmentation; Iterative algorithms; Parallel processing; Process design; Throughput;
Conference_Titel :
Pattern Recognition, 1990. Proceedings., 10th International Conference on
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-8186-2062-5
DOI :
10.1109/ICPR.1990.119391