• DocumentCode
    3382182
  • Title

    A novel variation insensitive clock distribution methodology

  • Author

    Hussein, E.E.O. ; Ismail, Yehea I.

  • Author_Institution
    Nano-Electron. Integrated Syst. Center (NISC), Nile Univ., Cairo, Egypt
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    1743
  • Lastpage
    1746
  • Abstract
    A new clock distribution technique is introduced in this paper. The technique avoids repeaters completely and distributes the clock directly on the passive interconnect network. The wires can be highly lossy, yet the clock is delivered with a very good shape and eye. The technique uses the characteristics of the interconnect to attenuate all frequency components equally. The resulting clock at the sinks does not depend on supply variations at all and only depends on the LC time constant of the wires. Interestingly, the technique works even better with higher clock frequencies. Signal equalization and boosting at the clock source is applied to further improve the clock shape at the receivers.
  • Keywords
    clock distribution networks; integrated circuit design; passive networks; boosting; clock shape; passive interconnect network; signal equalization; variation insensitive clock distribution methodology; Clocks; Delay; Frequency; Jitter; Power transmission lines; Propagation constant; Repeaters; Shape; Voltage; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537550
  • Filename
    5537550