A unipolar-CMOS with recessed source/drain load

In this study, for the first time, we produce a unipolar-CMOS logic, by replacing each of the PMOS devices with a gate-controlled punchthrough NMOS. Such a new logic maintains the traditional advantages of CMOS fabrication while avoiding the need to fabricate large p-well region on chip; this can lead to an improved transistor density, especial in non-Si technologies. To validate the feasibility of this design theory, we use commercial TCAD tools to simulate and verify Unipolar-CMOS inverters, NAND gates, NOR gates, and static random-access memory (SRAM). In each case, the simulation results show that the Unipolar-CMOS logic functions correctly. Moreover, this new logic is scalable to the Deca-Nanometer range, because the gate-controlled punchthrough NMOS is not significantly affected by the short channel effect. Owing to its superior integration-density and fabrication process, the Unipolar-CMOS technology can not only maintain but also go beyond the Moore´s law.