Title :
Analysis of multiple cell upsets due to neutrons in SRAMs for a Deep-N-well process
Author :
Mahatme, Nihaar ; Bhuva, Bharat ; Fang, Y.-P. ; Oates, Anthony
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Vanderbilt Univ., Nashville, TN, USA
Abstract :
This work accounts for the single-bit and multiple-cell upset phenomena due to neutron strikes in highly scaled SRAMs implemented in a Deep-N-well process. 3D TCAD simulations are used to explain test results, upset mechanisms and implications for ECC.
Keywords :
SRAM chips; error correction codes; neutrons; technology CAD (electronics); 3D TCAD simulations; SRAM; deep-N-well process; error correction code; multiple cell upsets; neutrons; Bipolar transistors; Error correction codes; Layout; MOSFETs; Neutrons; Random access memory; SRAMs; Soft-Error Rate; multiple-bit upset (MBU); multiple-cell upset (MCU); single-bit upset (SBU);
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2011.5784599
