Title :
A Ku-band down-converter with perfect differential PLL in 0.18um CMOS
Author :
Miyashita, Kiyoshi
Author_Institution :
Design & Dev. Center, Asahi-kasei Microdevices Corp., Atsugi, Japan
fDate :
May 30 2010-June 2 2010
Abstract :
This paper presents a Ku-band down converter that includes perfect differential PLL in a 0.18 μm CMOS technology. This front-end down-converts the input signal from the Ku-band (10.5~13 GHz) to the IF (~2.3 GHz). This fully integrated down-converter is dedicated to both satellite receivers and microwave link products. The perfect differential PLL shows very low supply voltage sensitivity (Kpss=-0.18[%/V]), making it possible to eliminate on chip regulator. A novel model-matched layout design methodology not only enhance ft but also reduce risk of non-convergences. The down converter performance include 5.5 dB gain; 4.35 dBm IIP3; -107 dBc/Hz phase noise at 1 MHz offset; 0.41 psec jitter; and current consumption is 102 mA from a 1.8 V supply.
Keywords :
CMOS integrated circuits; MMIC; convertors; phase locked loops; CMOS technology; Ku-band down-converter; chip regulator; current 102 mA; current consumption; differential PLL; front-end down-converter; full integrated down-converter; gain 5.5 dB; jitter; low supply voltage sensitivity; microwave link; model-matched layout design methodology; phase noise; satellite receivers; size 0.18 mum; voltage 1.8 V; CMOS integrated circuits; CMOS process; Phase frequency detector; Phase locked loops; Phase noise; Power supplies; Radio frequency; Satellite broadcasting; Semiconductor device modeling; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537556
