A high performance clock precharge SEU hardened flip-flop

Saving power consumption is the most important aspect of nanoscale ASIC and system-on-chips (SOCs). At the same time, due to the low supply voltage and reduced node capacitance, nanoscale integrated circuits are highly susceptible to energetic particle-induced transient data upsets (SEUs). In this paper, we propose a high-speed SEU hardened flip-flop. The flip-flop consists of a unique soft error robust storage (SERS) latch, a novel input transfer unit, and a unique two-input output buffer. With the rising edge of the clock, the transfer unit provides a narrow time window that passes the data to the SERS latch. The latch stores the data values at two storage nodes and two redundant nodes. The two-input output buffer, which is driven by the two storage node of the same logic, masks the propagation of any transient to the output. Post-layout simulations in 65nm CMOS technology show that the flip-flop exhibits as much as 52% lower power-delay product and 25% less area compared to recently reported soft error robust flip-flops.