Title :
Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter
Author :
Mei, Fengna ; Wang, Pengjun
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
Abstract :
Through the study of mixed-valued coding theory, the working principle of adiabatic circuits and up-down counters, a new design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter is proposed. Firstly, the functional expressions of 2-3 mixed-valued/six-valued adiabatic shift right gate and carry/borrow circuit are derived by using the theory of three essential circuit elements, then MOS transistors with different thresholds are adopted to achieve the corresponding structures, and 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter is further designed on this basis. Finally, HSPICE simulation results verifies correct logic function of the designed circuits, compared with 2-3 mixed-valued /six-valued asynchronous up-down counter, power consumption of the circuits saves up to 94%.
Keywords :
MOSFET; asynchronous circuits; carry logic; HSPICE simulation; MOS transistors; adiabatic asynchronous up-down counter; adiabatic circuits; adiabatic shift right gate; carry/borrow circuit; essential circuit elements; functional expressions; logic function; mixed-valued coding theory; six-valued coding theory; Flip-flops;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157271