DocumentCode
3382430
Title
Low noise low power two-stage modulator with injection locked LO divider in 65nm CMOS
Author
Wang, Wufeng ; Jiang, Peichen ; Mo, Tingting ; Zhou, Jianjun
Author_Institution
Center for Analog/RF Integrated Circuits (CARFIC), Shanghai Jiao Tong Univ., Shanghai, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
590
Lastpage
593
Abstract
This paper presents a two-stage modulator for low noise and low power design. The modulator is driven by LO and 2LO; by rejecting noise from the LO path, the modulator achieves a noise floor of -161dBc/Hz at an offset frequency of 40MHz. The modulator also enables the use of a low power injection locked frequency divider (ILFD) to generate quadrature LO. Supplied by 1.2V, the whole circuit consumes only 7.6mA. The modulator is designed in a 65nm CMOS process.
Keywords
CMOS integrated circuits; frequency dividers; injection locked oscillators; integrated circuit design; low-power electronics; modulators; CMOS process; LO path; current 7.6 mA; frequency 40 MHz; injection locked LO divider; low noise low power two-stage modulator; low power injection locked frequency divider; noise floor; offset frequency; quadrature LO; size 65 nm; voltage 1.2 V; Frequency modulation; Thermal noise;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157274
Filename
6157274
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