Research and implementation of random test generator for VLIW DSPs

Functional verification is a crucial step in the design of any electronic device. A new random test program generator has been developed for the functional verification of VLIW DSPs. The generator contains an independent formal model of the VLIW DSP architecture, which contains an instruction library and a resource manager to realize parallel operations and a heuristic function library of testing expertise to realize the constraints of instruction sequences. It has been used in the functional verification of several VLIW DSPs for 6 months by designers and testing engineers in our laboratory. Testing results show that the new generator can give better quality tests and shorten the functional verification period significantly.