An 80×80 general-purpose digital vision chip in 0.18μm CMOS technology

Author

Lopich, Alexey ; Dudek, Piotr

Author_Institution

Sch. of Electr. & Electron. Eng., Univ. of Manchester, Manchester, UK

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

4257

Lastpage

4260

Abstract

In this paper we present an implementation of the asynchronous/synchronous processor array (ASPA2) - a digital SIMD vision chip. The chip has been fabricated in a 0.18 μm CMOS process and comprises 80×80 array of pixel processors. The architecture of the chip is overviewed, the design of the processing cell is presented and implementation issues are discussed. At 75 MHz ASPA2 demonstrates 373 GOPS/W power and 871 MOPS/mm² area efficiency, making it suitable for the design of high speed and low power vision systems.

Keywords

CMOS digital integrated circuits; image sensors; intelligent sensors; low-power electronics; microprocessor chips; CMOS technology; asynchronous-synchronous processor array; digital SIMD vision chip; general-purpose digital vision chip; high speed vision system design; low power vision systems; pixel processor arrays; size 0.18 mum; smart image sensors; CMOS process; CMOS technology; Centralized control; Clocks; Decoding; Image processing; Image sensors; Logic devices; Machine vision; Process design;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537565

Filename

5537565