A simplified approach for designing secure Random Number Generators in HW

This paper presents a method to design a Random Number Generator (RNG), which is a fundamental element in cryptographic and other security related systems. The proposed RNG implementation is based on a Gollmann cascade of Filtered Feedback with Carry Shift Register (FFCSR) cores and is suitable for a wide range of applications. In order to comply with the demands of most applications the RNG must have low hardware cost and power dissipation, and be suitable for real time operation while maintaining a high level of security. In the proposed solution, elementary F-FCSR components are modularly combined to fit the RNG for the desirable application. The RNG will produce a pseudo-random sequence with suitable period, linear complexity and statistical quality. Simulations performed using the statistical test suite available through NIST, show that the proposed RNG holds good statistical properties, a secure mathematical structure and meets known standards.