• DocumentCode
    3382636
  • Title

    Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster

  • Author

    Shin, Dongsuk ; Cho, Joo-Hwan ; Choi, Young-Jung ; Chung, Byoung-Tae

  • Author_Institution
    Graphics Memory Design Team, Hynix Semicond. Inc., Icheon, South Korea
  • fYear
    2010
  • fDate
    27-29 Sept. 2010
  • Firstpage
    79
  • Lastpage
    82
  • Abstract
    A fast-lock all-digital register-controlled delay-locked loop (RCDLL) with wide-range duty cycle adjuster is presented. The architecture of the proposed fast-lock RCDLL uses the initial delay monitor without the delay line, which shares with the register controlled delay line for high accuracy of initial delay. Also, the duty cycle corrector of the DLL has achieved wide correction range to a small delay of the duty cycle adjuster. The proposed RCDLL with wide-range duty cycle adjuster has been designed with a 0.18um CMOS process and operates over a frequency range from 250MHz to 1.2GHz with a 1.8V supply voltage. The lock-time of the DLL is 10cycles independent to the input frequency.
  • Keywords
    CMOS integrated circuits; delay lock loops; CMOS process; duty cycle corrector; fast-lock RCDLL; fast-lock all-digital register-controlled delay-locked loop; frequency 250 MHz to 1.2 GHz; frequency range; frequency-independent fast-lock register-controlled DLL; initial delay monitor; input frequency; lock-time; register controlled delay line; size 0.18 mum; supply voltage; voltage 1.8 V; wide-range duty cycle adjuster; Clocks; Delay; Delay lines; Mixers; Monitoring; Temperature measurement; Temperature sensors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOC Conference (SOCC), 2010 IEEE International
  • Conference_Location
    Las Vegas, NV
  • ISSN
    Pending
  • Print_ISBN
    978-1-4244-6682-5
  • Type

    conf

  • DOI
    10.1109/SOCC.2010.5784640
  • Filename
    5784640