Software BIST capabilities of a symmetric cipher

Cryptographic devices have to be fully testable in order to ensure proper functionalities. On the other hand, security requirements restrict the use of some testing techniques, such as scan chains. Built-In Self Tests may be a solution, but they often require expensive additional components included into the circuitry. The possibility of using the ciphering circuit itself to perform the self test has been proposed. In this paper, we further explore this approach and we analyze the configuration parameters that affect the fault coverage. We show that achieving 100% coverage is less easy than previously published.