Title :
A high-speed asynchronous array multiplier based on multi-threshold semi-static NULL convention logic pipeline
Author :
Yang, Yanfei ; Yang, Yintang ; Zhu, Zhangming ; Zhou, Duan
Author_Institution :
Dept. of Microelectron., XiDian Univ., Xi´´an, China
Abstract :
This paper proposes an asynchronous 12 × 12 -bit array multiplier. Firstly, we proposed a new asynchronous pipeline of which data processing and completion detection can be carried out simultaneously by applying multi-threshold semi-static NCL (MTSNCL) to asynchronous combinational logic. Sencondly, the pipeline is used for designing an asynchronous 12 × 12 -bit array multiplier. Finally, both the proposed array multiplier and the original array multiplier are simulated based on SMIC 0.18-μm CMOS technology. Compared with the general asynchronous array multiplier, the new array multiplier has 76.5% higher throughput, 43.8% lower TDD cycle time and 38.7% lower static power consumption. The multi-threshold array multiplier is suitable for high-speed lower-power asynchronous multiplier design.
Keywords :
CMOS logic circuits; asynchronous sequential logic; combinational circuits; high-speed integrated circuits; CMOS technology; asynchronous combinational logic; asynchronous pipeline; high-speed asynchronous array multiplier; multithreshold semi-static NULL convention logic pipeline; size 0.18 mum; Arrays; CMOS integrated circuits; CMOS technology; Fabrication; Logic arrays; Logic gates; Pipelines;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157285