Title :
Clock buffer with duty cycle corrector
Author :
Kao, Shao-Ku ; You, Yong-De
Author_Institution :
Dept. of Electr. Eng., Chang Gung Univ., Taoyuan, Taiwan
Abstract :
A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or maintain duty cycle of input clock. It corrects the input duty cycle of 10% ~ 90% for generated 50% duty cycle of output clock. Moreover, it enhances the input clock signal driving ability and keeps duty cycle the same as duty cycle of input clock with range from 20% ~ 80%. The proposed circuit operation frequency range is from 100 MHz ~ 1 GHz. The proposed circuit has been fabricated in a 0.18 um CMOS technology.
Keywords :
CMOS integrated circuits; buffer circuits; clocks; CMOS technology; clock buffer; duty cycle corrector circuit; input clock signal; Area measurement; CMOS integrated circuits; Clocks; Pulse measurements;
Conference_Titel :
SOC Conference (SOCC), 2010 IEEE International
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-6682-5
DOI :
10.1109/SOCC.2010.5784648
