Clock buffer with duty cycle corrector

A clock buffer with duty cycle corrector circuit is presented. The proposed circuit can generate either 50% duty cycle or maintain duty cycle of input clock. It corrects the input duty cycle of 10% ~ 90% for generated 50% duty cycle of output clock. Moreover, it enhances the input clock signal driving ability and keeps duty cycle the same as duty cycle of input clock with range from 20% ~ 80%. The proposed circuit operation frequency range is from 100 MHz ~ 1 GHz. The proposed circuit has been fabricated in a 0.18 um CMOS technology.