A 55nm 1GHz one-cycle-locking de-skewing circuit

This paper presents the design of a 55nm 1.0V 1GHz open-loop de-skewing circuit for clock synchronization in a SoC. All-digital architecture and circuit design techniques are adopted and developed to achieve small jitter, low power, super fast locking, and input duty-cycle independence. Even running at 1 GHz, the proposed circuit wakes up from sleep with only one-cycle locking time. Measurement results show a peak-to-peak jitter of 4 ps and a static phase error of 5.46 ps at 1 GHz. To the best of our knowledge, this is the first GHz open-loop de-skewing circuit achieving sub-μW/MHz active power. By power gating, 84% of leakage power is saved in the sleep mode.