A 70dB SNDR 10-MHz BW hybrid delta-sigma/pipeline ADC in 0.18-µm CMOS

The Leslie-Singh structure is often used in low oversampling, high bandwidth applications. A new hybrid delta-sigma/pipeline ADC extends this architecture via multi-rate signal processing to allow the pipelined ADC to run at a lower sampling frequency. With an NTF that is designed to match part of the corresponding decimation filters´ coefficients, additional power and silicon area saving is achieved. Quantization noise coupling is used to save one integrator. Implemented in a 0.18-μm CMOS process, the 12X OSR ADC provides 70-dB SNDR with a 10-MHz signal bandwidth with DAC calibration.