DocumentCode
3382824
Title
Single Fault Models for Timed FSMs
Author
Uyar, M. Ümit ; Wang, Yu ; Batth, Samrat S. ; Wise, Adriana ; Fecko, Mariusz A.
Author_Institution
Dept. of Electr. Eng., New York Univ.
Volume
3
fYear
2005
fDate
16-19 May 2005
Firstpage
2349
Lastpage
2354
Abstract
The classification and detection of single timing faults in timed FSMs are introduced. A graph augmentation method is used to formulate the detection models for timing faults. It is shown that, by using our graph augmentation models, a faulty IUT ends up in a different state than the intended one, hence, enabling the detection of these single timing faults
Keywords
conformance testing; fault diagnosis; finite state machines; graph theory; fault detection; graph augmentation method; single fault models; single timing faults; timed FSM; Automata; Automatic testing; Cities and towns; Computer science; Costs; Educational institutions; Fault detection; Protocols; Timing; Upper bound; Conformance Testing; Fault Modeling; Simple Faults; Timed Automata; Timer Constraints;
fLanguage
English
Publisher
ieee
Conference_Titel
Instrumentation and Measurement Technology Conference, 2005. IMTC 2005. Proceedings of the IEEE
Conference_Location
Ottawa, Ont.
Print_ISBN
0-7803-8879-8
Type
conf
DOI
10.1109/IMTC.2005.1604598
Filename
1604598
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