Title :
Area efficient LDPC decoder design for parallel layered decoding
Author :
Yao, Yuan ; Ye, Fan ; Ren, Junyan
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
An area efficient LDPC decoder hardware design for parallel layered decoding algorithm is proposed. Shift register chain is used to reduce the chip area. Puncturing technique is employed to produce arbitrary rate between 1/2 and 1. This design is implemented based on rate-1/2 LDPC in 802.16e with 65nm CMOS. The decoder achieves a throughput of 1.2 Gb/s at 10 iterations with an area of 1.14mm2 and support any rate between 1/2 and 1.
Keywords :
CMOS logic circuits; decoding; parallel algorithms; parity check codes; shift registers; CMOS; area efficient LDPC decoder hardware design; bit rate 1.2 Gbit/s; chip area; low density parity check code; parallel layered decoding algorithm; puncturing technique; shift register chain; size 65 nm; Bismuth; Clocks; Decoding; Random access memory; 802.16e; LDPC decoder; parallel layered decoding algorithm; quasi-cyclic codes; shift register chain;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157296
