Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness

SRAM Bit-Cell Sleep technique is extensively used in processors to minimize SRAM leakage power. However, magnitude of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper analyzes influence of design parameters like VCCMIN_RET, DVS, ITD and NBTI on effectiveness of SRAM bit-cell sleep scheme. Impact of Process Technology on SRAM bit-cell sleep scheme effectiveness, due to transition from SiO₂ to Hafnium based High-K gate dielectric material is also discussed in this paper. Silicon measurement results of a 3MByte SRAM array designed in 32nm High-K CMOS process is used to demonstrate diminishing effectiveness of SRAM bit-cell sleep technique.