Title :
Process technology and design parameter impact on SRAM Bit-Cell Sleep effectiveness
Author :
Shamanna, Guru ; Kshatri, B.S. ; Gaurav, R. ; Tew, Y.S. ; Marfatia, P. ; Raghavendra, Y. ; Naik, V.
Author_Institution :
Intel® Corp., Bangalore, India
Abstract :
SRAM Bit-Cell Sleep technique is extensively used in processors to minimize SRAM leakage power. However, magnitude of leakage power savings from SRAM bit-cell sleep technique is dependent on process technology and various design parameters. This paper analyzes influence of design parameters like VCCMIN_RET, DVS, ITD and NBTI on effectiveness of SRAM bit-cell sleep scheme. Impact of Process Technology on SRAM bit-cell sleep scheme effectiveness, due to transition from SiO2 to Hafnium based High-K gate dielectric material is also discussed in this paper. Silicon measurement results of a 3MByte SRAM array designed in 32nm High-K CMOS process is used to demonstrate diminishing effectiveness of SRAM bit-cell sleep technique.
Keywords :
CMOS memory circuits; SRAM chips; hafnium; high-k dielectric thin films; integrated circuit measurement; memory architecture; microprocessor chips; power aware computing; DVS design parameter; Hafnium based high-k gate dielectric material; ITD design parameter; NBTI design parameter; SRAM array design; SRAM bit-cell sleep technique; SRAM leakage power minimization; design parameter impact; high-k CMOS process; leakage power saving; process technology; silicon measurement; size 32 nm; Arrays; Floors; Leakage current; Logic gates; Random access memory; Sleep; Transistors;
Conference_Titel :
SOC Conference (SOCC), 2010 IEEE International
Conference_Location :
Las Vegas, NV
Print_ISBN :
978-1-4244-6682-5
DOI :
10.1109/SOCC.2010.5784653
