DocumentCode
3382993
Title
Analysis and architecture design of aggregation in BM3D
Author
Liu, Wenjiang ; Zhu, Yue ; Liu, Tao ; Rong, Mengtian ; Zhang, Hao
Author_Institution
Dept. of Electr. Eng., Shanghai Jiao Tong Univ., Shanghai, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
703
Lastpage
706
Abstract
BM3D (Block-Matching and 3D Filtering) [1] [2] algorithm has the best performance of denoising so far. BM3D algorithm, which is a general Image/Video denoising algorithm, takes good use of the spatial correlation of the image and temporal correlation of the video. BM3D algorithm includes three steps: the first is Block-Matching, the second is 3D-Filtering, and the third is Aggregation. As for Block-Matching, several papers about H.264 encoding have introduced this method [3] [4] [5]. For 3D denoising, many good algorithms have been introduced [6]. But for aggregation issue, nothing has been discussed about ASIC architecture implementation. In this paper, we propose a solution that can effectively realize aggregation.
Keywords
application specific integrated circuits; correlation methods; filtering theory; image denoising; image matching; video coding; 3D denoising; 3D filtering algorithm; ASIC architecture implementation; BM3D algorithm; H.264 encoding; aggregation; architecture design; block-matching algorithm; image denoising algorithm; spatial correlation; temporal correlation; video denoising algorithm; Algorithm design and analysis; Bandwidth; Clocks; Matched filters; Static VAr compensators; Time frequency analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157302
Filename
6157302
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