Title :
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform
Author :
Hou Hui ; Cao Wei ; Zhang Fan-jiong ; Lai Jin-mei ; Tong Jia-rong
Author_Institution :
State Key Lab. of ASIC, Fudan Univ., Shanghai
fDate :
Aug. 31 2008-Sept. 3 2008
Abstract :
Two dimensional discrete wavelet transform (2DDWT) has been adopted as a coding tool of JPEG 2000 image coding and MPEG-4 still texture coding. To make it suitable for real-time image processing applications, it is essential to develop custom VLSI chips for computation of 2D-DWT. A new high efficient architecture is proposed for 2D 1-level DWT, with the feature of original data is scanned by group and no temporal buffer is needed. Comparison results show our proposed architecture can provide a higher speed at less hardware consume.
Keywords :
VLSI; digital signal processing chips; discrete wavelet transforms; image processing; integrated memory circuits; 2D 1-level discrete wavelet transform; VLSI chips; high-speed architecture; memory-efficient architecture; Computer architecture; Data flow computing; Discrete wavelet transforms; Filters; Hardware; Image coding; Image processing; MPEG 4 Standard; Memory architecture; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
DOI :
10.1109/ICECS.2008.4674896
