DocumentCode
3383052
Title
Low power design for SoC with power management unit
Author
Sun, Daying ; Xu, Shen ; Sun, Weifeng ; Lu, Shengli ; Shi, Longxing
Author_Institution
Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
719
Lastpage
722
Abstract
In this paper, motivated by reducing power consumption of system-on-chip (SoC), sets of methods are applied in low power design for SoC, especially power management unit integrated. Corresponding to different applications, different power supply is provided. The whole SoC has been implemented with SMIC 0.13um standard CMOS process, the test results show that the operating frequency is 100MHz and the power consumption is about 96.24 mW.
Keywords
CMOS integrated circuits; low-power electronics; power electronics; system-on-chip; CMOS process; SoC; frequency 100 MHz; low power design; power consumption; power management unit; size 0.13 mum; system-on-chip; Indexes; Phasor measurement units; Random access memory; Routing; Switches; System-on-a-chip; Time frequency analysis; DC-DC converter; LDO converter; System-on-chip (SoC); dynamic power consumption; power management unit (PMU);
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157306
Filename
6157306
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