Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography

Based on the research of the theories and circuits of (2ⁿ) GF Galois Field multiplier and X multiplier, this paper presented the reconfigurable architecture for Galois Field multiplier, which use GF(2⁸) as basic field and GF[(2⁸)]⁴ as extension field. The architecture could flexibly and efficiently support different Galois Field multipliers, such as GF(2⁸), GF[(2⁸)]², GF[(2⁸)]³ and GF[(2⁸)]⁴. The design had been realized using Altera´s FPGA and synthesized and optimized on Synopsys´s Design Compiler. The result proved that the maximum frequency could achieve 260MHz on 0.13μm CMOS technology.