DocumentCode
3383143
Title
Associating packets of heterogeneous cores using a synchronizer wrapper for NoCs
Author
Matos, Débora ; Carro, Luigi ; Susin, Altamiro
Author_Institution
Inst. de Inf., PPGC Fed. Univ. of Rio Grande do Sul-UFRGS, Porto Alegre, Brazil
fYear
2010
fDate
May 30 2010-June 2 2010
Firstpage
4177
Lastpage
4180
Abstract
MPSoCs systems are composed of heterogeneous cores, and for this reason, the cores can present different bandwidth, different clock domains or still they can require an irregular traffic behavior. When networks-on-chip (NoCs) are used to connect these cores, one very often needs some synchronization solution, and due to the mentioned problems, this might be required for synchronous or asynchronous NOCs. In this paper we show a network interface (NI) with a synchronizer wrapper solution. We verified its applicability for different channel widths and buffer depths of a NoC. These network interfaces were used to connect a H.264 decoder and the simulation results demonstrate that the wrapper provides a reliable synchronization solution, and does not compromise the latency of the network. These interfaces have been successfully implemented in a 0.18um CMOS technology.
Keywords
CMOS digital integrated circuits; network interfaces; network-on-chip; synchronisation; CMOS technology; H.264 decoder; MPSoC systems; NoC; heterogeneous core packets; network interface; network-on-chip; size 0.18 mum; synchronization solution reliability; synchronizer wrapper solution; Bandwidth; CMOS technology; Clocks; Decoding; Delay; Network interfaces; Network-on-a-chip; Proposals; Synchronization; Telecommunication traffic;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location
Paris
Print_ISBN
978-1-4244-5308-5
Electronic_ISBN
978-1-4244-5309-2
Type
conf
DOI
10.1109/ISCAS.2010.5537596
Filename
5537596
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