DocumentCode :
3383238
Title :
H-tree CMOS logic circuit
Author :
Cheng, Shun-Wen
Author_Institution :
Dept. of Electron. Eng., Far East Univ., Tainan
fYear :
2008
fDate :
Aug. 31 2008-Sept. 3 2008
Firstpage :
542
Lastpage :
545
Abstract :
Programmable routing networks and configurable logic blocks (CLB) achieve configurable computing of nowadays. This study proposed a novel H-tree configurable circuit. The 10-transistor (5P5N) CMOS version H-tree logic gate can generate AOI22, OAI22, AOI21, OAI21, NAND3, NAND2, NOR3, NOR2 and INV functions. A classic 8-to-1 multiplexer-based logic module needs 36 transistors to implement these functions; even an Actelpsilas ACT 1 logic module also needs 24 transistors to cover the job. Both the transistor count and layout cost of the proposed configurable gate are smaller than any other logic cell in FPGA/CPLD. The configurable logic gate could work with the existing logic cells to increase gate utilization and integration.
Keywords :
CMOS logic circuits; field programmable gate arrays; logic design; logic gates; network routing; Actel ACT 1 logic module; FPGA-CPLD; H-tree CMOS logic circuit; configurable logic blocks; field-programmable gate arrays; multiplexer-based logic module; programmable routing network; CMOS logic circuits; Costs; Field programmable gate arrays; Input variables; Logic circuits; Logic functions; Logic gates; Multiplexing; Table lookup; Wires; CMOS logic; VLSI; configurable computing; configurable logic; configurable logic block (CLB);
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on
Conference_Location :
St. Julien´s
Print_ISBN :
978-1-4244-2181-7
Electronic_ISBN :
978-1-4244-2182-4
Type :
conf
DOI :
10.1109/ICECS.2008.4674910
Filename :
4674910
Link To Document :
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