Title :
A single-event upset hardening technique for high speed MOS Current Mode Logic
Author :
Haghi, Mahta ; Draper, Jeff
Author_Institution :
Electr. Eng. Dept., Univ. of Southern California, Los Angeles, CA, USA
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, we introduce a SEU-hard MOS Current Mode Logic (MCML) sequential element that is used in high speed communication systems. We have implemented latches and flip-flops in 65 nm technology and show that the critical charge needed to upset the sensitive nodes in these circuits is increased with this proposed design. Simulation has been conducted for clock rates of 0.5, 1, 2 and 4 GHz. The results show the critical charge increases more than 5 times (>440%) with this design while the delay (32 ps) is acceptable for GHz operations.
Keywords :
MOS logic circuits; current-mode logic; flip-flops; logic design; sequential circuits; MCML sequential element; flip-flops; frequency 4 GHz; high speed communication systems; high-speed MOS current mode logic; latches; single-event upset hardening technique; size 65 nm; Circuit noise; Clocks; Crosstalk; Flip-flops; Frequency; Latches; Logic; Power dissipation; Single event upset; Voltage;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537603
