An innovative sub-32nm SRAM voltage sense amplifier in double-gate CMOS insensitive to process variations and transistor mismatch

Author

Nasalski, Piotr ; Makosiej, Adam ; Giraud, Bastien ; Vladimirescu, Andrei ; Amara, Amara

Author_Institution

DMCS, Tech. Univ. of Lodz, Lodz

fYear

2008

fDate

Aug. 31 2008-Sept. 3 2008

Firstpage

554

Lastpage

557

Abstract

This paper introduces a novel voltage sense amplifier (VSA) in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Three different architectures are described and their operation margins are analyzed as a function of transistor length (L) and threshold voltage (Vth) variations and mismatch. The proposed architecture takes advantage of the back gate to enhance feedback and add more input nodes to provide a faster (25%-40%) and more insensitive to mismatch (100%-300%) circuit.

Keywords

CMOS integrated circuits; SRAM chips; amplifiers; silicon-on-insulator; SRAM voltage sense amplifier; double-gate CMOS; planar independent self-aligned gates; process variations; silicon-on-insulator technology; threshold voltage; transistor length; transistor mismatch; CMOS process; Capacitance; Circuit simulation; Feedback; MOS devices; MOSFETs; Monte Carlo methods; Random access memory; Threshold voltage; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 2008. ICECS 2008. 15th IEEE International Conference on

Conference_Location

St. Julien´s

Print_ISBN

978-1-4244-2181-7

Electronic_ISBN

978-1-4244-2182-4

Type

conf

DOI

10.1109/ICECS.2008.4674913

Filename

4674913