A new fast cell re-sequence mechanism for multipath ATM switches

Author

Heo, Jeong Won ; Sung, Dan Keun

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea

Volume

3

fYear

1999

fDate

1999

Firstpage

1814

Abstract

A new cell re-sequence mechanism is proposed to restore cell sequence in multipath ATM switches. Since the proposed mechanism uses per-VC logical queues which store only the cells belonging to the same VC, the mechanism can reduce processing time compared to conventional re-sequence mechanisms. The mechanism also has no limitation on the peak rate of the VCs and no arbitration functions to select an output cell. The mechanism can be implemented using a RAM buffer, a CAM/RAM table, a controller, etc

Keywords

asynchronous transfer mode; buffer storage; content-addressable storage; electronic switching systems; packet switching; queueing theory; random-access storage; CAM/RAM table; RAM buffer; cell sequence restoration; controller; fast cell re-sequence mechanism; multipath ATM switches; output cell selection; per-VC logical queues; processing time reduction; virtual channels; Asynchronous transfer mode; Buffer storage; CADCAM; Computer aided manufacturing; Delay; Fault tolerance; Switches; Timing; Traffic control; Virtual colonoscopy;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 1999. ICC '99. 1999 IEEE International Conference on

Conference_Location

Vancouver, BC

Print_ISBN

0-7803-5284-X

Type

conf

DOI

10.1109/ICC.1999.765576

Filename

765576