A reconfigurable linear array processor architecture for data parallel and computation intensive applications

Author

Liu, Yucheng ; Xie, Ling ; Mao, Zhigang

Author_Institution

Dept. of Microelectron., Shanghai Jiao Tong Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

783

Lastpage

786

Abstract

Recent embedded systems have switched to parallel microprocessors. Linear array processors and 2-D array processors are two classifications for the processing element (PE) interconnection. The former have better expansibility and greater throughput while the later have better communication efficiency. In order to improve the communicat ion efficiency without losing expansibility, this paper introduces RLAP, a reconfigurable linear array processor architecture, targeted at data parallel and computation intensive applications in the video domain. Compared with the conventional linear array processors, the performance of RLAP improves by 8.7 times, 104% and 10.8% for the applications of 8×8 matrix transpose, 8×8 DCT and 16×16 SAD.

Keywords

microprocessor chips; parallel architectures; 2D array processors; computation intensive application; data parallel application; embedded systems; parallel microprocessors; processing element interconnection; reconfigurable linear array processor architecture; Clocks; Computer architecture; Discrete cosine transforms; Program processors;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157322

Filename

6157322