Power analysis for Asynchronous CLICHÉ Network-on-Chip

Asynchronous Chip-Level Integration of Communicating Heterogeneous Elements (CLICHÉ) architecture is proposed to achieve low power Network-on-Chip (NoC). Asynchronous design could reduce the power dissipation of the network if the activity factor of the data transfer between two switches (α_data) satisfies a certain condition. The area of Asynchronous CLICHÉ switch is increased by 25% as compared to the Synchronous switch. However, the power dissipation of the Asynchronous architecture could be decreased by 21% as compared to the power dissipation in the conventional Synchronous architecture when the (α_data equals 0.2 and the activity factor of the control signals is equal to 1 over 64 of the (α_data. The total metal resources required to implement Asynchronous design is decreased by 7%.