A permutation network for configurable and scalable FFT processors

In this paper, we propose a permutation network, a key component for configurable and scalable FFT processors, to perform a set of permutations on streaming data. The method presented for constructing such permutation networks applies to permutations that can be represented as linear mappings on the bit representation of data location. The permutation network, consisting of several independent RAM blocks and two interconnection networks, is capable of operating in a pipelined way. To reduce the hardware complexity of permutation network significantly, a streaming architecture is adopted. Simulation is performed to verify the correctness of permutation network and implementation results are given.