DocumentCode
3383592
Title
Power minimization methodology for VCTL topologies
Author
Ekekon, Osman Kubilay ; Maltabas, Samed ; Margala, Martin ; Cilingiroglu, Ugur
Author_Institution
Univ. of Massachusetts Lowell, Lowell, MA, USA
fYear
2010
fDate
27-29 Sept. 2010
Firstpage
330
Lastpage
333
Abstract
In this work, power minimization method for Varicap Threshold Logic (VcTL) implementations is proposed. In this aspect, characteristics of NMOS and PMOS capacitances are investigated. AND-OR gates and full adder (FA) are selected to prove the proposed methodology in IBM 65 nm CMOS technology. It was found that the proposed methodology always provides the minimum power with 48% power savings in OR, 46% in FA and 9% in AND realizations compared to not optimized versions. It is shown that 0.8V supply voltage provides best PDP results for AND-OR topologies.
Keywords
CMOS integrated circuits; adders; capacitance; logic design; logic gates; threshold logic; AND-OR gates; CMOS technology; NMOS capacitance; PMOS capacitance; VCTL topology; full adder; power minimization methodology; size 65 nm; varicap threshold logic; voltage 0.8 V; Handheld computers; Integrated circuits; MOS devices;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference (SOCC), 2010 IEEE International
Conference_Location
Las Vegas, NV
ISSN
Pending
Print_ISBN
978-1-4244-6682-5
Type
conf
DOI
10.1109/SOCC.2010.5784688
Filename
5784688
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