Hybrid MOSFET/CNFET based power gating structure

This paper proposes a new hybrid MOSFET /carbon nanotube FET (CNFET) power gating structure using 32nm technology at a low voltage (0.6V). The power gating structure is one of the most effective methods to reduce the power dissipation of systems in sleep mode, but it suffers from increased propagation delay due to the high threshold voltage of power switches in the low voltage region. In this paper, to reduce the propagation delay of the power gating structure while keeping low leakage power in the sleep mode, the CNFETs are deployed as a power switch. This hybrid structure reduces the time gap in switching over from silicon MOSFET to CNFET technology. For a trade-off between wake-up overhead and leakage power saving, a four-power-mode PG structure using back-gate biasing of the CNFET switches is also proposed. The simulation results are compared to those of the MOSFET power gating designed 32nm technology.