A new low power symmetric folded cascode amplifier by recycling current in 65nm CMOS technology

A new low power symmetric folded cascode amplifier is presented. The proposed amplifier delivers the same performance as that of the conventional symmetric folded cascode amplifier while consuming only 50% the power. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in SMIC standard 65nm CMOS process. Simulation results show that the proposed amplifier achieves almost twice the bandwidth (313.4MHz versus 158.2MHz), 8.2dB DC gain enhancement (63.4dB versus 55.2dB) and better than twice the slew rate (45.6V/us versus 20.5V/us) compared to the conventional symmetric folded cascode amplifier with the same power. On the other hand, the power consumption of the proposed amplifier can reduce 50% compared to the conventional symmetric folded cascode amplifier with the same performance.