An efficient VLSI architecture for extended variable block sizes motion estimation

Video Coding using enlarged block sizes is one of the major technologies for the current developing High-performance Video Coding standard. In this paper, a novel VLSI architecture for full-search extended variable block sizes motion estimation is proposed. Adopting Macroblock SAD partition and partial SAD values reuse scheme, the proposed architecture employs PE numbers with same magnitude of current architectures to conduct motion estimation with block sizes from 4× to 64×64 pels while keeping high PE utilization. In consequence, this new architecture offers a feasible solution to next generation HVC standard.