• DocumentCode
    3383730
  • Title

    Design of cost-efficient multipliers modulo 2a−1

  • Author

    Piestrak, Stanislaw J.

  • Author_Institution
    IRISA/ENSSAT, Lannion, France
  • fYear
    2010
  • fDate
    May 30 2010-June 2 2010
  • Firstpage
    4093
  • Lastpage
    4096
  • Abstract
    In this paper, we propose a new design method for modulo 2a-1 multipliers which accept double representation of 0 of input operands. The new multiplier takes advantage of the symmetric properties of integers written in l´s complement representation which allows to reduce the size of carry-save adders (CSAs) used. Currently, for small a they are the least complex (in terms of the number of logic gates) multipliers modulo 2a-1 available in the open literature.
  • Keywords
    adders; logic design; CSA; carry-save adders; cost-efficient multipliers modulo 2a-1; design method; Adders; Calculus; Circuits; Convolutional codes; Design methodology; Digital arithmetic; Digital signal processors; Error correction codes; High performance computing; Logic gates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
  • Conference_Location
    Paris
  • Print_ISBN
    978-1-4244-5308-5
  • Electronic_ISBN
    978-1-4244-5309-2
  • Type

    conf

  • DOI
    10.1109/ISCAS.2010.5537626
  • Filename
    5537626
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3383730